•L1 (n = 20), L2 (n = 300) et MEM (n=1000)
•
•
Based on 195 MHz IP27
•
MIPS R10000 CPU
•
CPU revision 2.x
•
Typical Minimum Maximum
• Event Counter
Name
Counter Value Time
(sec) Time (sec) Time (sec)
•===============================================================================================================
• 0 Cycles.................................................. 9967721904 51.116523 51.116523 51.116523
•16 Cycles.................................................. 9967721904 51.116523 51.116523 51.116523
•25 Primary data cache
misses............................... 102640 0.004742 0.001484 0.004742
•26 Secondary data cache
misses............................. 6736 0.002608 0.001705 0.002902
•23 TLB
misses..............................................
16
0.000006
0.000006
0.000006
•
• 0 Cycles.................................................. 14893075584 76.374747 76.374747 76.374747
•16 Cycles.................................................. 14893075584 76.374747 76.374747 76.374747
•25 Primary data cache
misses............................... 895811520 41.391086 12.954813 41.391086
•23 TLB
misses.............................................. 78112 0.027275 0.027275 0.027275
•26 Secondary data cache
misses............................. 40160 0.015549 0.010166 0.017300
•
• 0 Cycles.................................................. 1235928224 6.338093 6.338093 6.338093
•16 Cycles.................................................. 1235928224 6.338093 6.338093 6.338093
•25 Primary data cache
misses............................... 73945232 3.416649 1.069362 3.416649
•26 Secondary data cache
misses............................. 1135920 0.439805 0.287533 0.489319
•23 TLB
misses.............................................. 44192 0.015431 0.015431 0.015431